###############################################################################
## @copyright Copyright (c) 2022 OnMicro Corp.
## @brief     T-head's E902 SoC simulator environment.
## @author    wei.lu@onmicro.com.cn
## @license   SPDX-License-Identifier: Apache-2.0
###############################################################################
SOC          = e902

# Test case list is src_c or in prebuilt/th_e902/: [src_c, coremark_v1.0]
CASE         = src_c

# Simulator: [iverilog, verilator, vcs]
SIM          = iverilog
# Dump waveform: [off, on]
DUMP         = off

# Common verilog sources of T-head E902 SoC.
SIM_FILELIST  = -f ../../../ip/cpu/e902/e902.fl
SIM_FILELIST += -f ../../../ip/soc/thead_soc902/soc902.fl

# Test bench verilog sources and includes.
SRC_DIR      += ./src_v
SIM_FILELIST += -y ../src_v/modules

# Test Case stimulus file.
INC_DIR += ./$(CASE)
ifeq ($(CASE),coremark_v1.0)
  TIMEOUT = off
endif

EXTRA_VFLAGS = ASIC

# Testbench verilog file list.
ifeq ($(SIM),verilator)
SIM_FILELIST += ../src_cc/sim_main.cpp
endif

# Common logic to run simulator.
include ../common/Makefile.sim

# Generate program memory pattern to load by simulator.
vmem: | $(PROJECT_DIR)
ifeq ($(CASE),src_c)
	make -C src_c CC=riscv64-unknown-elf-gcc V=0
	riscv-nuclei-elf-objcopy -O srec src_c/out/wujian100_open_evb.elf $(PROJECT_DIR)/rom.srec
else
	riscv-nuclei-elf-objcopy -O srec ../../prebuilt/e902/$(CASE).elf $(PROJECT_DIR)/rom.srec
endif
	../../tool/python/srec2vmem.py -i $(PROJECT_DIR)/rom.srec -o $(PROJECT_DIR)/rom.mem
